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DRAM: Architectures, Interfaces, and Systems

DRAM: Architectures, Interfaces, and Systems

There are two technologies for manufacturing RAM: static and dynamic, they each have their field of application

The SRAM or Static RAM is the oldest. The bits y are memorized by electronic flip-flops whose production requires six transistors per bit to be memorized. The information remains stored until the component is switched on. The motherboards use an SRAM constructed in CMOS technology and equipped with a battery to keep the configuration data (setup) of the BIOS in a non-volatile manner. The circuit of this CMOS RAM is associated with the clock circuit which also needs the battery to operate continuously even when the computer is turned off. The SRAM is very fast and is for this reason the type of memory used for cache memories.

The DRAM for dynamic RAM is much simpler than the SRAM. This makes it possible to make components with a higher density and a lower cost.

Each bit of a DRAM is stored by an electrical charge stored in a small capacitor. This device offers the advantage of being very little bulky but has the disadvantage of not being able to keep the information for a long time. The capacitor discharges after a few milliseconds (ms). Also in order not to lose the bit of information it contains, a device is required which reads the memory and rewrites it to recharge the capacitors. These RAMs are called dynamic RAMs because this refresh operation must be repeated regularly.

Table of contents

  • Basics
  • DRAM organization
  • Storage element
  • Switching element
  • DRAM Evolution: Structural Path
  • Advanced Basics
  • Bus transmission
  • Memory controller
  • Memory array
  • Memory and CPU
  • Data transfer
  • Physical organization
  • DRAM Evolution: Interface Path
  • Read Timing for Conventional DRAM
  • Read Timing for Fast Page Mode
  • Future Interface Trends & Research Areas
  • Performance Modeling:
  • Architectures, Systems, Embedded
  • Clocking Issues
  • SDRAM Topology Example
  • Access Protocol
  • SDRAM Chip
  • Technology Roadmap
  • DRAM Configurations
  • DDR2 Study Results

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Submitted On: 2016-12-31
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