CPU Architecture Tutorial

This document discusses history of the 80x86 CPU family and the major improvements occuring along the line.

The historical background will help you better understand the design compromises they made as well as understand the legacy issues surrounding the CPU s design. This chapter also discusses the major advances in computer architecture that Intel employed while improving the x86.

Table of contents

• Chapter Overview
• The History of the 80x86 CPU Family
• A History of Software Development for the x86
• Basic CPU Design
• Patch Panel Programming
• Encoding Instructions
• Encoding Instructions with Source and Destination Fields
• Decoding and Executing Instructions: Random Logic Versus Microcode
• RISC vs. CISC vs. VLIW
• Instruction Execution, Step-By-Step
• Parallelism – the Key to Faster Processors
• The Prefetch Queue – Using Unused Bus Cycles
• CPU Design with a Prefetch Queue
• Pipelining – Overlapping the Execution of Multiple Instructions
• A Typical Pipeline
• A Pipelined Implementation of Instruction Execution
• Instruction Execution in a Pipeline
• Stalls in a Pipeline
• Instruction Caches – Providing Multiple Paths to Memory
• A Typical Harvard Machine
• Using Separate Code and Data Caches
• A Data Hazard
• How the 80x86 Handles a Data Hazard
• A CPU that Supports Superscalar Operation
• Parallel Processing
• Multiprocessing

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Created:	2017-01-02

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